The present invention relates generally to semiconductor integrated circuit devices, and more particularly to semiconductor integrated circuit having precharge circuits suitable for use in high speed applications.
Conventional semiconductor integrated circuits generally use a precharge circuit for performing high speed operations. The precharge circuit is controlled, based on a clock signal, to alternately have a precharge period and an active period. A latch circuit is typically arranged previous to a precharge circuit for latching an input signal. Generally, a level trigger type latch circuit is used for that purpose, where a through period for passing an input signal therethrough and a hold period for holding an input signal are alternately controlled by a clock signal.
For example, a latch circuit is controlled to have a through period for passing an input signal therethrough when a clock signal .phi.1 for controlling the latch circuit is at high level and to enter a hold period for holding data latched therein at the time the clock signal .phi.1 changes to a low level. Also, a precharge circuit is controlled, for example, to have a precharge period when a clock signal .phi.2 for controlling the precharge circuit is at low level and to have an active period for operating in response to an input signal supplied thereto at the time the clock signal .phi.2 changes to a high level.
The clock signal .phi.1 and the clock signal .phi.2 have the same period and opposite phases to each other such that the latch circuit and the precharge circuit operate in synchronism. In other words, the latch circuit is in a through period when the clock signal .phi.1 is at high level, while the precharge circuit is in a precharge period since the clock signal .phi.2 is in opposite phase, i.e., at low level. When the clock signal .phi.1 changes to low level to cause the latch circuit to enter a hold period to hold an input signal, the clock signal .phi.2 is in opposite phase, i.e., at high level, causing the precharge circuit to enter an active period, in which the precharge circuit operates based on the signal held in the latch circuit.
Since the clock signal .phi.1 used to control the latch circuit and the clock signal .phi.2 used to control the precharge circuit have the same period and opposite phases to each other, these circuits suffer from a dead time due to a phase difference skew. How a phase difference skew occurs is explained below in detail.
The clock signal .phi.1 and the clock signal .phi.2 should have the same period and opposite phases to each other, so that, essentially, when the clock signal .phi.1 changes from high level to low level, the clock signal .phi.2 must change from low level to high level at the same timing. Conversely, when the clock signal .phi.1 changes from low level to high level, the clock signal .phi.2 must change from high level to low level at the same timing. However, since the clock signal .phi.1 and the clock signal .phi.2 are different clock signals, they are typically generated and distributed by different circuits. Therefore, variations in the processes and devices used for generating these clocks may cause a deviation in timing between a rising edge of the clock signal .phi.1 and a falling edge of the clock signal .phi.2, i.e., a phase difference skew.
When a rising edge of the clock signal .phi.2 is delayed from the timing of a falling edge of the clock signal .phi.1 to arise a phase difference skew, the operation of the precharge circuit is delayed due to the delayed rising edge of the clock signal .phi.2, although the latch circuit has performed a latch operation in response to the falling edge of the clock signal .phi.1, thus arising a dead time corresponding to the delay of the clock signal .phi.2.
Conversely, when the clock signal .phi.2 goes high earlier than a falling edge of the clock signal .phi.1 to arise a phase difference skew, the clock signal .phi.2 goes high even during a through period of the latch circuit, in which the latch circuit is not yet performing a latch operation, to cause the precharge circuit to operate in response to the rising clock signal .phi.2. Thus, the precharge circuit cannot perform a correct operation, and a dead time arises corresponding to the time by which the clock signal .phi.2 has risen earlier than the falling edge of the clock signal .phi.1.
Further, since the phase difference skew possibly occurs when the clock signal .phi.2 goes high at the timing of a falling edge of the clock signal .phi.1 and when the clock signal .phi.1 goes high at the timing of a falling edge of the clock signal .phi.2, the phase difference skew can occur twice in one cycle of the clock signal .phi.1, thus resulting in a longer dead time.
With the ever increasing miniaturization of semiconductor integrated circuits, discrete circuits can operate at higher speeds. However, as a total load capacity and a total wiring length associated with clock signals are increased due to higher integration of semiconductor integrated circuits, it is more difficult to reduce the clock skew, particularly, the phase difference skew as compared with discrete circuits.
When a precharge circuit is employed, for example, in each of a plurality of logical circuits which are connected in series for performing high speed logical operations within one machine cycle, the logical operations must be performed so as to avoid a dead time due to the above-mentioned phase difference skew, and a latch circuit must be operated to store data indicating the results of the logical operations before the next dead time occurs. For these requirements, the number of stages of the serially connected logical circuits must be reduced to perform a less number of logical operations within one machine cycle. Thus, although the precharge circuit is employed for the purpose of high speed operations, the high speed operations are limited by the influence of the dead time due to the phase difference skew.